DocumentCode :
2245143
Title :
An Efficient Realization of the Decision Feedback Equalizer using Block Floating Point Arithmetic
Author :
Shaik, Rafiahamed ; Chakraborty, Mrityunjoy
Author_Institution :
Dept. of E & ECE, Indian Inst. of Technol., Kharagpur
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
1047
Lastpage :
1050
Abstract :
An efficient scheme is presented for implementing the decision feedback equalizer (DFE) in block floating point (BFP) format, which permits processing of data over a wide dynamic range at a processor cost marginally higher than that of a fixed point processor. It uses block processing of the input which is block formatted by an appropriate algorithm, taking care so that there is no overflow at the feed forward filter output and also that a uniform BFP representation of the input data vector is available all throughout including the inter-block transition phase. Suitable steps are also taken for block formatting the data used in computation of the feedback filter output, again ensuring no overflow. As the computations involve mostly fixed point based operations, considerable saving in computational complexities is achieved, as against a conventional floating point based realization
Keywords :
decision feedback equalisers; floating point arithmetic; BFP representation; block floating point arithmetic; block formatting; block processing; computational complexities; data processing; decision feedback equalizer; interblock transition; Costs; Decision feedback equalizers; Dynamic range; Electronics packaging; Feeds; Field-flow fractionation; Filters; Floating-point arithmetic; Intersymbol interference; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342268
Filename :
4145576
Link To Document :
بازگشت