Title :
The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter
Author :
Chiang, Jen-Shim ; Chiang, Ming-Da
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Abstract :
An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 μm CMOS process. The core area occupies 1450 μm×1100 μm. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; operational amplifiers; pipeline processing; 0.35 micron; 1.5 V; 10 MHz; 10 bit; 15 mW; CMOS process; analog/digital converter; dynamic comparators; low-power operation; low-voltage ADC; pipelined ADC; power consumption; switched op amp; switched operational amplifiers; Analog-digital conversion; CMOS process; Digital circuits; Energy consumption; Integrated circuit technology; Low voltage; Operational amplifiers; Power amplifiers; Sampling methods; Switches;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857126
