Efficient error-cancelling algorithmic ADC

Author

Zheng, Z. ; Min, B. ; Moon, U. ; Temes, G.

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

451

Abstract

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme together with the correlated double sampling (CDS) technique, the virtually error-free and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in applications which require low-cost medium-speed and high-resolution A/D conversion

Keywords

CMOS integrated circuits; analogue-digital conversion; error compensation; signal sampling; 0.18 micron; 1.8 V; 16 bit; 4 mW; capacitor mismatch; correlated double sampling technique; differential sampling scheme; double-poly CMOS process; error compensation; error-cancelling algorithmic ADC; fast multiply-by-two operation; finite opamp gain; high-resolution A/D conversion; opamp gain and offset; Capacitors; Circuits; Clocks; Computer errors; Costs; Data conversion; Moon; Sampling methods; Signal processing algorithms; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857128

Filename

857128