A high accuracy-low complexity model for CMOS delays

Author

Casu, M.R. ; Masera, G. ; Piccinini, G. ; Roch, M. Ruo ; Zamboni, Maurizio

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

Volume

1

fYear

2000

fDate

2000

Firstpage

455

Abstract

This paper presents a new model for CMOS structures delays estimation based on a deep analysis of complex gates behavior. This approach can supply a high level of accuracy. A complex structure is reduced first to series-connected MOS, then the delay equations are applied to that reduced rate. The model is based on a time piecewise linearization so that a strongly nonlinear circuit can he solved using well known linear techniques. The delay formulas involve model parameters as MOS width functions, therefore providing routines suitable for optimization algorithms. The high level of accuracy, the low CPU time and the high degree of scaling capability are proved in the paper. These features make the model attractive for deep submicron technologies

Keywords

CMOS digital integrated circuits; CMOS logic circuits; circuit analysis computing; circuit optimisation; delay estimation; integrated circuit modelling; logic gates; piecewise linear techniques; timing; CMOS delays; MOS timing macromodel; MOS width functions; complex gate behavior; deep submicron technologies; delay equations; delays estimation; high accuracy-low complexity model; model parameters; nonlinear circuit; optimization algorithms; scaling capability; series-connected MOS; time piecewise linearization; CMOS technology; Capacitance; Circuits; Computational complexity; Delay; Electronic mail; Nonlinear equations; Semiconductor device modeling; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857129

Filename

857129