Selective TiSi2 by CVD, one step further

Summary form only given. Some of the problems to be overcome within ULSI technology are those related to the contact metallization over very shallow junctions. The scalability of sub-0.5 /spl mu/m CMOS devices imposes a junction depth of the order of 0.1 to 0.15 /spl mu/m to minimize the short channel effect and punchthrough current. Consequently, active area metallization requirements make it more difficult to use metal silicides, since thin layers are associated with poor contact and sheet resistance. The investigation of contact materials is permanent in order to have a self-aligned contact scheme in the sub-0.5 /spl mu/m regime. TiSi/sub 2/ formed by self-aligned silicide (SALICIDE) technology, has for some considerable time been practically the best candidate due to the low resistivity, good adhesion and thermal stability. Several studies have been published on the application of this technology in ULSI circuits down to design rules of 0.25 /spl mu/m and below. However, some drawbacks are still reported with the standard salicide like substrate consumption, dopant redistribution and film agglomeration which make necessary some complementary steps such as preamorphization by ion implantation or thin metal layer deposition. Using CVD we have already shown several benefits of TiSi/sub 2/ silicidation from the vapor phase. An industrial cluster reactor at reduced pressure and temperature has obtained selective deposition, lower contact resistance and higher saturation current, low sheet resistance on poly bars independently of the line width down to 0.2 /spl mu/m as well as a one step process which increases throughput.