Title :
Improving simulation efficiency for circuit-level power estimation [CMOS]
Author :
Marculescu, Radu ; Ababei, Cristinel
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
In this paper we present an effective technique for compacting a large sequence of input vectors into a much shorter one so as to reduce the circuit-level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, we model the effects of complex spatiotemporal correlations and rise/fall time slopes on total power dissipation. As the results demonstrate, large compaction ratios of orders of magnitude can be obtained without significant loss (about 5%, on average) in the accuracy of power estimates
Keywords :
CMOS integrated circuits; Markov processes; circuit simulation; integrated circuit design; low-power electronics; circuit-level power estimation; circuit-level simulation time; compaction ratios; input vector sequence; rise/fall time slopes; simulation efficiency; spatiotemporal correlations; total power dissipation; Circuit simulation; Compaction; Computational modeling; Energy consumption; Maintenance engineering; Power dissipation; Power engineering computing; Power generation; Spatiotemporal phenomena; Statistics;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857134
