DFM-aware Routing for Yield Enhancement

Author

Hong, Xianlong ; Cai, Yici ; Yao, Hailong ; Li, Duo

Author_Institution

Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1091

Lastpage

1094

Abstract

As EDA industry advances to smaller and smaller technology nodes, a tighter link between VLSI circuit manufacturing and physical design is becoming a necessity. This paper introduces several design for manufacturability (DFM) related problems such as critical area reduction, redundant via insertion, chemical-mechanical polishing (CMP), etc. Then the corresponding DFM-aware routing problems are formulated and solved using the proposed routing algorithms, respectively. Experimental results show that great yield enhancement can be obtained with a little runtime burden in routing, which proves the feasibility and effectiveness of considering DFM issues during the routing stage

Keywords

VLSI; chemical mechanical polishing; design for manufacture; network routing; CMP; DFM aware routing; critical area; design for manufacturability; redundant via; runtime burden; yield enhancement; Chemical technology; Circuits; Computer science; Design for manufacture; Electronic design automation and methodology; Manufacturing industries; Routing; Runtime; Tiles; Very large scale integration; CMP; DFM; critical area; redundant via; routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342311

Filename

4145587