A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits

An exact fault simulation can be achieved by simulating only the faults on reconvergent fanout stems, while determining the detectability of faults on other lines by critical path tracing within fanout-free regions. The authors have delimited, for every convergent fanout stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected at the line, and the line is critical with respect to a primary output, then the stem fault is detected at the primary output. Any fault-simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. Results obtained for the well-known benchmark circuits are presented.<>