Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC

In this paper, the authors propose a novel high-throughput, ASIC architecture to realize the context-adaptive variable-length decoder (CAVLC) of H.264/AVC baseline profile. The authors conduct a thorough analysis of inherent parallelism of the CAVLC algorithm and identify particular steps that will benefit from parallel computing. In particular, the authors adopt a bit-position VLC decoding approach to decode multiple symbols concurrently in a critical step in CAVLC. This modification leads to almost 40% reduction of clock cycles compared to a straight-forward implementation