DocumentCode
2246270
Title
A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding
Author
Lin, Chia-Chun ; Lin, Yu-Kun ; Chang, Tian-Sheuan
Author_Institution
Inst. of Electron., Nat. Chiao-Tung Univ., HsinChu
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1248
Lastpage
1251
Abstract
The paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling and mode filtering that reduces the computing complexity of integer ME by 75%, and only two modes instead of various modes are refined for fractional ME. This also can save about 80% fractional ME cycle counts in average. The simulation result shows that it only increases the bit rate within 2% and at most 0.14dB quality degradation. Finally, the resulted parallel architecture only costs 58% of area cost and requires 48% of cycle counts when compared with the previous designs
Keywords
motion estimation; video coding; MPEG-4 AVC/H.264 video coding; fast algorithm; fractional ME; mode filtering; motion estimation; parallel architecture; Automatic voltage control; Bit rate; Computational modeling; Computer architecture; Costs; Filtering algorithms; Hardware; MPEG 4 Standard; Motion estimation; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342389
Filename
4145626
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