A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter

In this paper, we propose a high throughput and data reuse architecture for de-blocking filter in H.264/AVC. There are two SRAMs exploited in the design. One is 144times32 bits single-port SRAM, and the other is 16times32 bits two-port SRAM. We use the group-of-pixel access method to store the pixels in SRAMs instead of the column-of-pixel or row-of-pixel approach. In the algorithm level, we modify the filtering order in the de-blocking filter without violating the H.264/AVC standard. Therefore, we efficiently use the data reuse skill to reduce the access frequency of SRAMs. We implement this architecture with UMC 0.18 mum cell library, and the maximum clock frequency we can achieve is 100 MHz. The simulation results show that the total number of logic gate counts is 16.6k. When the clock frequency equals 100 MHz, it can process 14619 macroblocks in 1/30 second. In other words, we achieve 4XGA (2048times1536) @30 frames/sec when we set the clock frequency to 85 MHz