Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search

In this paper, associative memory architecture for a fully parallel nearest Euclidean distance search is proposed. It uses digital circuitry up to subtraction and absolute value calculation in the vector-component comparator part. Analog processing is then applied up to completion of the winner-take-all function. From HSPICE simulation in 0.35 mum CMOS technology the authors confirmed that the winner is detected in less than 135 nsec and the average power dissipation is less than 220 mW among 64 reference patterns each representing a 16-dimensional vector with 5 bit components. A test chip is also designed in 0.35 mum CMOS technology and the chip size is 5.12 mm with 2-poly and 3-metal layers for nearest Euclidean distance search