DocumentCode :
2246736
Title :
An experimental study on the package stress in plastic encapsulated IC (integrated circuit)
Author :
Lee, Minju ; Joo, Won-Gu
Author_Institution :
Adv. Semicond. Eng., Inc., Kyunggi-Do, South Korea
fYear :
2001
fDate :
2001
Firstpage :
268
Lastpage :
273
Abstract :
Transfer molding is the primary process for IC (integrated circuit) encapsulation with EMC (epoxy molding compound) and also the most extensive method for plastic packaging. Plastic encapsulated packages offer many advantages over their other counterparts such as low cost, light weight, and ready availability that accounted for approximately 98% of IC packages produced within the microelectronics industry. The recent trends in plastic packaging are packages becoming thinner and smaller where drawbacks are more serious in terms of package stress from the transfer molding process. It is for this reason that the need for thorough understanding of package stress is becoming greater. In this paper, flow-induced package stress is experimentally visualized to analyze time-dependence flow characteristics of EMC by employing different geometrical gate design parameters. Also, EMCs with different material properties are evaluated to quantify their influence on package stress in terms of interfacial adhesion, warpage, voiding, wire sweep, and penetration rate. In addition, screening DOE (design of experiments) is performed to identify the main process parameters, and the optimum window of critical parameters is defined by RSM (response surface methodology)
Keywords :
adhesion; design of experiments; encapsulation; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit packaging; internal stresses; moulding; plastic packaging; stress analysis; surface fitting; voids (solid); EMC; EMC material properties; EMC time-dependence flow characteristics; IC encapsulation; IC packages; RSM; design of experiment; epoxy molding compound; flow-induced package stress; geometrical gate design parameters; interfacial adhesion; microelectronics industry; optimum critical parameter window; package availability; package cost; package stress; penetration rate; plastic encapsulated IC; plastic encapsulated package; plastic packaging; process parameters; response surface methodology; screening DOE; transfer molding; transfer molding process; voiding; warpage; wire sweep; Costs; Electromagnetic compatibility; Encapsulation; Microelectronics; Plastic integrated circuit packaging; Plastic packaging; Plastics industry; Stress; Transfer molding; Visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging, 2001. EMAP 2001. Advances in
Conference_Location :
Jeju Island
Print_ISBN :
0-7803-7157-7
Type :
conf
DOI :
10.1109/EMAP.2001.983996
Filename :
983996
Link To Document :
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