An experimental study on the package stress in plastic encapsulated IC (integrated circuit)

Transfer molding is the primary process for IC (integrated circuit) encapsulation with EMC (epoxy molding compound) and also the most extensive method for plastic packaging. Plastic encapsulated packages offer many advantages over their other counterparts such as low cost, light weight, and ready availability that accounted for approximately 98% of IC packages produced within the microelectronics industry. The recent trends in plastic packaging are packages becoming thinner and smaller where drawbacks are more serious in terms of package stress from the transfer molding process. It is for this reason that the need for thorough understanding of package stress is becoming greater. In this paper, flow-induced package stress is experimentally visualized to analyze time-dependence flow characteristics of EMC by employing different geometrical gate design parameters. Also, EMCs with different material properties are evaluated to quantify their influence on package stress in terms of interfacial adhesion, warpage, voiding, wire sweep, and penetration rate. In addition, screening DOE (design of experiments) is performed to identify the main process parameters, and the optimum window of critical parameters is defined by RSM (response surface methodology)