DocumentCode
2246952
Title
A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages
Author
Elraba, M.E.S. ; Anis, Mohab H. ; Elmasry, Mohamed I.
Author_Institution
Dept. of Electr. Eng., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Volume
1
fYear
2000
fDate
2000
Firstpage
748
Abstract
A new contention-free domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 μm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area are also presented
Keywords
CMOS logic circuits; SPICE; integrated circuit noise; leakage currents; logic simulation; low-power electronics; 0.25 micron; 2.5 V; HSPICE; area; contention-free domino logic; dynamic power; leakage power; noise margin; scaled-down CMOS technologies; speed; ultra low threshold voltages; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Clocks; Degradation; Low voltage; MOS devices; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.857204
Filename
857204
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