• DocumentCode
    2246971
  • Title

    Low-power data-driven dynamic logic (D3L) [CMOS devices]

  • Author

    Rafati, R. ; Fakhraie, S. Mehdi ; Smith, K.C.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    752
  • Abstract
    In this paper a new family of low-power dynamic logic called data-driven dynamic logic (D3L) is introduced. In this logic family, the synchronization clock has been eliminated, and correct sequencing is maintained by appropriate use of data instances. Then, it is shown that replacement of the clock with input data implies less power dissipation without speed degradation compared to conventional dynamic logic
  • Keywords
    CMOS logic circuits; low-power electronics; CMOS; D3L; data instances; data-driven dynamic logic; input data; low-power dynamic logic; power dissipation; speed degradation; CMOS logic circuits; Capacitance; Clocks; Degradation; Logic devices; Logic functions; Power dissipation; Pulse inverters; Routing; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
  • Conference_Location
    Geneva
  • Print_ISBN
    0-7803-5482-6
  • Type

    conf

  • DOI
    10.1109/ISCAS.2000.857205
  • Filename
    857205
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2246971