Single input current-sensing differential logic (SCSDL)

A new novel single input current-sensing differential logic (SCSDL) is proposed. The SCSDL is flexible-in particular high input Boolean logic functions can be implemented with low complexity, area consumption, time delay, and power consumption. The first part of the area saving comes from the remarkable reduction of wiring; the other part comes from the very low number of transistors needed to implement a complex Boolean function, compared with other types of logic (e.g. CRDL, CSDL, DCVSL, static logic). Since this logic relies on comparison of currents in two branches, mismatch could ruin the function. The yield of the logic is good for a high performance process referred to mismatch