Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design

This work introduces a new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of V_dd=0.1- 1.5V and V_th= 0 - 0.8V, are analyzed to find optimal V_dd and V_th. BSIMSOI3.3 model (level 57) is used to verify the answers. The authors show that energy-delay product (EDP) isn´t appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and the formulations for finding the optimum gate sizing are also presented. Theses algorithms can be implemented in a CAD tool too