Circuit Area-latency Optimization Technique for High-precision Elementary Functions

Hardware implementation of IEEE-754 double-precision elementary functions, such as square root, reciprocal, etc, requires search for a tradeoff between the logic gate/wire area and the look-up table area. In this paper, we propose a new technique to reduce both the look-up table size and access latency of IEEE-754 double-precision elementary functions. Simulations show that the optimization reduces the total memory requirements for five elementary functions by 1/50 while almost the same computation delay. The technique is simple yet suitable for the SoC design of arithmetic modules