Efficient Implementation of AES IP

The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance