DocumentCode
2247298
Title
Hybrid technology multithreaded architecture
Author
Gao, Guang ; Likharev, Konstantin K. ; Messina, Paul C. ; Sterling, Thomas L.
Author_Institution
Delaware Univ., Newark, DE, USA
fYear
1996
fDate
27-31 Oct 1996
Firstpage
98
Lastpage
105
Abstract
The objective of the hybrid technology multithreaded architecture (HTMT) research is to determine the feasibility and structure of a parallel architecture integrating the combined capabilities of semiconductor, superconductor, and optical technologies. This mix of technologies may yield operational attributes superior to those based solely on semiconductor technology. The authors present a brief overview of the crucial technology-the superconducting rapid single-flux quantum logic (RSFQ) technology, as well as the HTMT multithreaded program execution models and architecture. The HTMT approach exploits key emerging devices. Specifically, computational performance can be dramatically improved through recent advances in RSFQ technology, making 100 GHz clock rates feasible in the near future. Memory capacity may be drastically increased through a new memory hierarchy merging superconductor memory, advanced semiconductor high-density memory and future optical 3D holographic storage. Interconnection bandwidth will be greatly enhanced by means of optical networks with very high bandwidth
Keywords
holographic storage; parallel architectures; semiconductor storage; superconducting logic circuits; 100 GHz; advanced semiconductor high-density memory; clock rates; computational performance; hybrid technology multithreaded architecture; interconnection bandwidth; memory capacity; memory hierarchy; multithreaded program execution models; optical 3D holographic storage; optical networks; optical technology; parallel architecture; semiconductor technology; superconducting rapid single-flux quantum logic technology; superconductor memory; superconductor technology; Bandwidth; Clocks; Computer architecture; Holographic optical components; Holography; Integrated optics; Logic devices; Merging; Parallel architectures; Superconducting logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Frontiers of Massively Parallel Computing, 1996. Proceedings Frontiers '96., Sixth Symposium on the
Conference_Location
Annapolis, MD
ISSN
1088-4955
Print_ISBN
0-8186-7551-9
Type
conf
DOI
10.1109/FMPC.1996.558066
Filename
558066
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