Synthesis of Finite State Machines for Low Power and Testability

State encoding is an essential step for sequential circuit synthesis, especially when area, delay and/or power consumption are the main emphasis. Sequential circuits consume a considerable amount of power, as these are used to implement control circuitry, which remains always active even when some of the data-paths are shutdown. With the rapid advancement in VLSI technology and device miniaturization testing of these circuits is also getting equal importance. A unique scheme of testability measure is introduced to the proposed method and a trade-off is done for power and testability. All these key ideas - partitioning, state encoding and testability in the synthesis process and applied genetic algorithm (GA) have been included to find near optimal solution. It is found that average improvement in power consumption of 16.47% over NOVA when the weightage on testability is set to 0.2 and average fault coverage of 99.39% is achieved when the weightage is 0.8, which is superior to other synthesis tool such as NOVA