2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic

This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and resembles behavior of static CMOS. As a result, the delay time of the 2PADCL is shorter than that of the conventional ADCL circuit in the second and subsequent stages. The structure of 2PADCL can be also directly derived from static CMOS logic circuits. From the simulation results, we show that the energy consumption of the 2PADCL circuit is lower than those of other diode based adiabatic logic circuits