DocumentCode :
2247700
Title :
Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL)
Author :
Mrunal, A.K. ; Shirasgaonkar, M.A. ; Patrikar, Rajendra
Author_Institution :
Microelectron., Indian Inst. of Technol. Bombay, Mumbai
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
1488
Lastpage :
1491
Abstract :
The next generation of super-computers or base band circuits of advanced radio-telecommunication systems require very high speed switching circuits. Compound semiconductor materials such as gallium arsenide (GaAs) will play an important role in such systems. In GaAs devices the hole velocity is approximately 15-20 times lower compared to the electron velocity. This means that the complimentary structures are not as desirable in GaAs as they are in silicon. This leads to higher power consumption in these circuits. In this paper low power GaAs logic family stacked active load FET logic (SALFL) is proposed for the battery operated, portable wireless applications. In this proposed logic family, the ON and OFF state (leakage) currents are reduced using stacked active loads, there by reducing power consumption. GaAs circuits are preferred in high performance wireless front end circuits but are not used in base-band digital circuits due to their high current consumption and domination of silicon CMOS circuits in integrated circuit applications. But the CMOS technology already at 45nm node is plagued with the problem of sub-threshold leakage currents particularly severe in sub-100nm CMOS digital logic families. Both these problems can be effectively overcome using the GaAs SALFL logic family. Above low power technique is implemented with a standard enhancement/depletion mode FET processes and provides all the standard logic functions (Invertion, AND, OR, NOR, NAND etc) like other ( DCFL, SCF )logic families. This technique shows improved results with all GaAs devices like pHEMTs and MESFET. With this technique current consumption can be reduced while taking into account area requirements
Keywords :
CMOS logic circuits; digital integrated circuits; elemental semiconductors; gallium arsenide; high-speed integrated circuits; low-power electronics; silicon; 100 nm; 45 nm; CMOS circuits; CMOS digital logic families; GaAs; Si; base band circuits; base-band digital circuits; compound semiconductor materials; current consumption; dynamic power; high speed digital circuits; high speed switching circuits; integrated circuit; leakage currents; logic family; low power digital circuits; low power technique; power consumption; radio-telecommunication systems; stacked active load FET logic; stacked active loads; static power; super-computers; wireless front end circuits; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Digital circuits; Energy consumption; FETs; Gallium arsenide; Logic devices; Silicon; Switching circuits; DCFL; Dynamic Power; GaAs Digital Circuits; Low Power; Static Power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342504
Filename :
4145685
Link To Document :
بازگشت