Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

Author

Paul, Gopal ; Pradhan, Sambhu N. ; Pal, Ajit ; Bhattacharya, Bhargab B.

Author_Institution

Dept. of Comput. Sci. & Eng´´g, Indian Inst. of Technol., Kharagpur

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1504

Lastpage

1507

Abstract

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based synthesis technique using dual rail static differential cascode voltage switch with pass gate (DCVSPG) logic. The method yields around 22% reduction in number of MUX cells. Simulation result using SPICE on 180 nm technology with 1.5 volts supply shows, on an average, 65% reduction in power consumption for frequency ranging up to 1 GHz compared to the result with static CMOS logic. It is envisaged that the proposed approach is useful in realizing low-power circuits

Keywords

VLSI; binary decision diagrams; logic design; low-power electronics; 1.5 V; 180 nm; VLSI circuits; VLSI synthesis; VLSI testing; VLSI verification; binary decision diagrams; dual rail static DCVSPG logic; dual rail static differential cascode voltage switch with pass gate logic; low power BDD; low-power circuits; synthesis technique; Boolean functions; CMOS logic circuits; Circuit synthesis; Circuit testing; Data structures; Logic gates; Rails; Switches; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342508

Filename

4145689