A High-Speed Low-Complexity VLSI SISO Architecture

In this paper, different high-speed architectures for SISO block of a turbo decoder are explored, and a structure based on a new multiple window (MW) technique is proposed. The new high-speed and low-complexity architecture serves high-quality turbo-coding applications. According to the system-level simulation and architectural explorations on the area and speed of the implemented SISO block, the optimized size of internal memories and logic cells are determined. The architecture is described using VHDL modeling and synthesized for Altera´s FPGA platforms. The new SISO block is verified and compared with the various previously presented SISO blocks. The obtained results of synthesis for hardware area and speed complexities are presented to satisfy the proposed architecture design capabilities