High throughput memory data-path design for multi-core architecture

Network on chip (NoC) has been proposed as new on-chip communication paradigm for the multi-core processing era. But the memory wall problem is a design bottleneck, especially in real-time applications. This paper proposes a high throughput memory data-path design that can guarantee real-time I/O throughput for an in-house developed multi-core system. The main contribution is as follows: Firstly, a data path DMA controller between the local processing cores and the on chip communication network is designed. Once the data access is established, it can transfer one data per cycle. Secondly, pre-programmed mechanism is used to schedule data exchange to reduce more cycles of register configuration. The design was successfully implemented on FPGA with fade-in-fade-out real-time video application. Experiment results show that 1024-bit data can be transferred in only 51 cycles and the system can run at 90MHz.