• DocumentCode
    2248027
  • Title

    Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations

  • Author

    Juang, Tso-Bing

  • Author_Institution
    Dept. of Inf. Technol., Nat. Pingtung Inst. of Commerce
  • fYear
    2006
  • fDate
    4-7 Dec. 2006
  • Firstpage
    1539
  • Lastpage
    1542
  • Abstract
    In this paper, an area/delay efficient recoding method for parallel CORDIC (coordinate rotation digital computer) rotation algorithm is proposed. This recoding method can reduce the number of micro-rotation stages when the bit-width of input angle increases. The most critical path of the conventional CORDIC rotation lies in the determination of rotation directions, which depends on the sign of the remaining angle after each iteration. Our proposed method can also predict the rotation direction directly from the binary value of the initial input angle. Our proposed architectures have a more regular and simpler prediction scheme compared to previous approaches using non-parallel CORDIC rotation methods. The critical path delay of our proposed method is reduced compared with parallel CORDIC rotation method
  • Keywords
    VLSI; digital arithmetic; digital computers; logic design; parallel architectures; recording; CORDIC rotation methods; VLSI architecture; area/delay efficient recoding method; critical path delay; microrotation stages; parallel coordinate rotation digital computer rotation algorithm; Business; Concurrent computing; Delay; Helium; Information technology; Iterative algorithms; Matrix decomposition; Signal processing algorithms; Vectors; Very large scale integration; CORDIC; VLSI architecture; recoding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
  • Conference_Location
    Singapore
  • Print_ISBN
    1-4244-0387-1
  • Type

    conf

  • DOI
    10.1109/APCCAS.2006.342536
  • Filename
    4145698