Next generation dielectric etching technology

To develop and fabricate devices with a design rule below 100 nm in the SOC (System-On-a-Chip) era, we need a systematic methodology for process development and qualification. We also need an etch tool that is well-defined, and equipped with monitors. It must also have controlling software based on the scientific understanding of reactive plasma and of etch reactions. This tool will make possible the concurrent development of devices and their production processes with a quick TAT (Turn Around Time). One of the critical issues for future device manufacturing is high-aspect-ratio-pattern etching of ILD (Inter-Layer Dielectric materials), such as SiO/sub 2/ and low-k materials, using a CF (fluorocarbon) plasma. ASET Plasma Technology Laboratory adopted this CF plasma etching of SiO/sub 2/ and conducted a research project to understand the etch mechanism and to establish a basis for a systematic methodology, monitors, and modeling tools. It finished the mission successfully at the end of March 2001. This paper reviews the project and discusses about future plasma etching technologies.