Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance Values

Due to the high computational complexity of the full-search algorithm for video coding, techniques to accelerate the execution of the full-search algorithm are needed for realtime implementations of current video compression standards. In this paper, a technique of using eight-bit partial sums of four luminance values is proposed to reduce the computational complexity of the original full-search algorithm without loss of its accuracy. Furthermore, since the proposed technique is suitable for the implementation on the single instruction multiple data (SIMD) architectures, the byte-type data-parallelism of the SIMD architecture can be utilized to further accelerate the execution of the proposed technique. Simulation results for the benchmark video test sequences demonstrate that the proposed technique can significantly accelerate the execution of the full-search algorithm on SIMD architectures without loss of its accuracy