Using genetic algorithm for slicing floorplan area optimization in circuit design

The paper describes a combined genetic algorithm and slicing approach for floorplan area optimization. This approach helps the designer to explore the floorplan issues during the early stage of integrated circuit design. The slicing tree representation provides efficient tree traversal operations using recursion for obtaining area-efficient floorplans. Also, the slicing floorplan approach reduces the complexity of the resulting floorplan at the routing stage by eliminating the cyclic conflicts