Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN

The conventional design of channel equalizer for IEEE 802.11a wireless local area network (WLAN) does not consider the different requirements of the adopted modulation schemes. In this paper, an adaptive-modulation-oriented channel equalizer and its VLSI architecture are developed. We analyze the different computation efforts of the modulation schemes and consider the system-level adaptive-modulation technique in the hardware implementation of channel equalizer. The adaptive-modulation-oriented channel equalizer applied to IEEE 802.11a can provide the appropriate architectures for different modulation schemes. In order to save the hardware resource, a dual-mode coordinate rotation digital computer (CORDIC) processor is designed, which is reused to accomplish rectangular-to-polar conversion and phase correction. The simulations and an implementation using FPGA technology validate the design