Title :
Optimizing High Speed Flip-Flop Using Genetic Algorithm
Author :
Aezinia, Fatemeh ; Afzali-Kusha, Ali ; Lucas, Caro
Author_Institution :
Sch. of Electr. & Comput. Eng., Tehran Univ.
Abstract :
In this paper, the optimization of power-delay-product (PDP) of a high-speed flip-flop via transistor sizing is presented. The optimization is performed using the genetic algorithm (GA). The flip-flop which is used in this optimization is called modified hybrid latch flip-flop (MHLFF). The genetic algorithm is implemented in MATLAB with the fitness function expressed in terms of the power and the delay of the flip-flop. These parameters are accurately computed using Hspice for a 65nm CMOS technology. The results show a reduction of 31% in the PDP of the optimized structure compared to the flip-flop without any optimization
Keywords :
CMOS logic circuits; circuit optimisation; flip-flops; genetic algorithms; 65 nm; CMOS technology; MATLAB; fitness function; genetic algorithm; high speed flip-flop; modified hybrid latch flip-flop; power-delay-product; transistor sizing; CMOS technology; Circuits; Clocks; Degradation; Delay; Energy consumption; Flip-flops; Genetic algorithms; Latches; Logic; genetic algorithm; high speed flip-flop; optimization;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342165
