Cost effective signal generators for ADC BIST

ADC in SOC usually has no connection to the outside. Built-in self-test is a good way to verify this block´s performance. Stringent requirement of stimulus generator is the most important limitation of ADC BIST. Several methods of using stimulus with low linearity to test ADC with high linearity have been reported for standalone production test. These methods can be adapted for ADC BIST to reduce the BIST cost overhead. This paper investigates signal patterns that can be used in low cost BIST scheme. Two cost effective stimulus generator structures are presented. Simulation results shows that the generated signal with less than 7 bits linearity can be used to test a 16 bits ADC. The estimation errors of INL are less than 0.65 LSB.