Adaptive design for nanometer technology

Rising design uncertainties at advanced process nodes place conflicting demands on todays engineers. The widening safety-margins required to ensure robust designs in the face of such uncertainties lead to conservative designs with unacceptable power and performance overheads. On the other hand, low-power techniques such as dynamic voltage scaling (DVS) and clock-gating adversely affect circuit robustness. In this paper, we will review a number of techniques for adaptive design which mitigate the impact of margins by tuning system parameters (voltage and frequency) according to variations in runtime workload, environmental and process conditions. We will evaluate the margins that each of the different approaches require to guarantee correctness in the worst-case and typical operating point. We also propose a technique called Razor which is an aggressive method for eliminating all safety-margins through in situ error-detection and correction. Error-detection is achieved by a new type of Razor flip-flop that monitors critical path endpoints and flags timing errors upon detecting spurious transitions. Recovery is achieved through replay from a check-pointed state. We show the design of the transition-detecting Razor flip-flop and illustrate how it naturally detects SEU in combinational logic and inside latches. We present a 64 bit processor implementing Razor and show, on an average, 33% energy savings from our measurements on silicon.