Title :
Efficient VLSI-realizable decimators for sigma-delta analog-to-digital converters
Author :
Saramaki, Tapio ; Tenhunen, Hannu
Author_Institution :
Dept. of Electr. Eng., Tampere Univ. of Technol., Finland
Abstract :
The authors introduce a class of efficient linear-phase FIR (finite impulse response) decimators for attenuating the out-of-band noise generated by a sigma-delta modulator. These decimators contain no general multipliers and very few data memory locations, thereby making them easily realizable in CMOS VLSI. This is achieved by using several decimation stages, with each stage containing a small number of delays and arithmetic operations. The output sampling rate of these decimators is the minimum possible one, and the proposed decimators can be used, with very slight changes, for many oversampling ratios. Furthermore, these decimators highly attenuate the undesired out-of-band signal components of the input signal, thus significantly relaxing the antialiasing prefilter requirements.<>
Keywords :
CMOS integrated circuits; VLSI; analogue-digital conversion; digital filters; A/D convertors; CMOS VLSI; VLSI-realizable decimators; antialiasing prefilter requirements; digital filter; finite impulse response; linear phase FIR decimators; noise attenuation; output sampling rate; sigma-delta ADC; sigma-delta modulator; Analog-digital conversion; Arithmetic; Baseband; Delta-sigma modulation; Finite impulse response filter; Noise generators; Noise level; Noise reduction; Quantization; Sampling methods;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
DOI :
10.1109/ISCAS.1988.15220