A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor

Author

Lai, Chi-Chen ; Hwang, Wei

Author_Institution

Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., HsinChu

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1931

Lastpage

1934

Abstract

In this paper, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed processor is characterized with scalable power-consumption for different FFT/IFFT sizes. Unlike the general pipeline-based architectures which use a larger internal wordlength to achieve a high signal to noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while adopting the block-floating point (BFP) approach to maintain the SNR

Keywords

fast Fourier transforms; floating point arithmetic; microprocessor chips; pipeline processing; block-floating point approach; mixed-radix algorithm; pipeline-based architectures; reconfigurable mixed-radix FFT processor; reconfigurable mixed-radix IFFT processor; scalable power-consumption; signal to noise ratio; Computational complexity; Computer architecture; Costs; Discrete Fourier transforms; Equations; Fast Fourier transforms; Hardware; Information systems; Microelectronics; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342238

Filename

4145795