DocumentCode
2250212
Title
An exact algorithm for low power library-specific gate re-sizing
Author
Chen, De-Sheng ; Sarrafiadeh, M.
Author_Institution
Electron. Res. & Service Org., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
783
Lastpage
788
Abstract
In this paper we examine the problem of reducing the power consumption of a technology mapped circuit under timing constraints. Consider a cell library that contains multiple implementations (cells) of the same Boolean function. We first present an exact algorithm for the problem when a complete library is given in a complete library, “all” implementations of each cell are present. We then propose an efficient algorithm for the problem if the provided library is not complete
Keywords
Boolean functions; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; Boolean function; cell library; exact algorithm; low power library-specific gate re-sizing; multiple implementations; power consumption; technology mapped circuit; timing constraints; Boolean functions; Circuits; Clocks; Delay; Energy consumption; Libraries; Permission; Power dissipation; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545678
Filename
545678
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