A spread spectrum clock generator with spread ratio error reduction scheme for DisplayPort main link

In this paper, a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link is presented. The process variation compensator not only reduces the error of spread ratio but also guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been implemented in 0.18-mum CMOS process and supports 10-phase 270 MHz and 162 MHz output clock. The experimental results show that the average rms jitter of 270 MHz output clock is 4.7 ps without spread spectrum clocking. 8.75 dBm of the peak reduction and 5000 ppm of spread ratio with the process variation compensator are achieved.