Reducing power dissipation after technology mapping by structural transformations

Due to the increasing demand for low power circuits, low power dissipation has emerged as an important optimization goal in logic synthesis. In this paper, we show that the power dissipation of technology mapped circuits can be significantly reduced by ATPG-based structural transformations. Our approach performs a sequence of permissible signal substitutions, where each substitution reduces the power consumption of the circuit. Since timing constraints can be considered, we achieve a trade-off between power and delay. The effectiveness of the proposed method is based on two facts. First, the power models for library gates are reasonably accurate. Thus, the power savings achieved by transformations of mapped circuits are also well modeled. Second, ATPG-based structural transformations effectively exploit don´t care conditions after technology mapping even for large circuits. Experimental results show power reductions of 26% on average with no area penalty. Substantial power reductions are also achieved if timing constraints are considered