Title :
New approach in gate-level glitch modelling
Author :
Rabe, Dirk ; Nebel, Wolfgang
Author_Institution :
Dept. of Comput. Sci., Carl von Ossietzky Univ. Oldenburg, Germany
Abstract :
An enhanced gate-level glitch model for logic simulation is presented. This new approach can be used to enhance logic simulation accuracy and power estimation at little additional computation costs. The simulation algorithm is compatible with common event driven simulation models for glitch-free cases. Only if a possible glitch is detected the simulation is modified by our model. The model is based on common timing characterization data and a few additional constant values. The features of the model an enhanced scheduling of glitch events and prediction of glitch peak voltages, which are essential for precise power estimation
Keywords :
circuit analysis computing; digital simulation; logic CAD; logic circuits; accuracy; common timing characterization; event driven simulation; gate-level glitch model; logic simulation; power estimation; precise power estimation; Circuits; Delay; Dynamic scheduling; Energy consumption; Equations; Logic; Predictive models; Semiconductor device modeling; Threshold voltage; Variable structure systems;
Conference_Titel :
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Conference_Location :
Geneva
Print_ISBN :
0-8186-7573-X
DOI :
10.1109/EURDAC.1996.558079
