Design and Optimization of Self-Biased Complementary Folded Cascode

This paper presents design and optimization procedure of a self-biased complementary folded cascade. A self-biased scheme is chosen as a technique that saves power and circuit area, and is less sensitive to process variations. The gain of basic folded cascode is enhanced using a gain boosting approach based on common source self-biased amplifiers. The circuits are optimized using the global optimization approach with the cost function calculated by circuit simulations. The hybrid approach to optimization is used combining the global search strategy using particle swarm optimization (PSO) and direct pattern search (DPS) method used as local search strategy. A complementary folded cascode operational amplifier is designed in the 0.35 mum CMOS technology with the 3.3 V power supply voltage