A robust synchronized 2N2P LC oscillator with a shut-down mode for adiabatic logic circuits

Adiabatic logic saves energy compared to static CMOS by charging the outputs efficiently and by recovering charge from the outputs. For the most promising adiabatic logic families a four phase power-clock is used, that can be generated in an energy efficient manner by using a synchronized 2N2P LC oscillator. Different input patterns to the circuit lead to different capacitive loads seen by the oscillator. A method to investigate the impact of the pattern-induced capacitive variations on the LC oscillator is presented in this paper. The circuit should be disconnected from the power-clock in idle times, when no data is processed, as adiabatic logic consumes energy also if no change occurs in the input data. We propose an easy to implement, powerful and fast method to switch off the oscillator by holding the synchronization signals constant. This makes adiabatic systems even more energy efficient.