Predicting parallel computer speedup for array processing applications in simulation

Author

Lee, C.H.

Author_Institution

Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA

fYear

1993

fDate

1-3 Nov 1993

Firstpage

1623

Abstract

A typical array processing problem is run on parallel computers. A critical issue in using parallel computers is to maintain the speed up with respect to the increased number of processors. A VHDL simulation model was developed to predict the speed up of the parallel computer system. It is important to characterize the computation and communication work loads in the partition procedure. Ethernet prediction results are compared with running data. The accuracy of this model is satisfactory. The prediction of the speedup of a frequency domain beamformer is in progress

Keywords

array signal processing; digital simulation; parallel processing; specification languages; Ethernet prediction results; VHDL simulation model; array processing; communication work loads; frequency domain beamformer; parallel computer speedup; Application software; Array signal processing; Computational modeling; Computer simulation; Concurrent computing; Costs; Ethernet networks; Frequency domain analysis; Hardware; Message passing; Military computing; Predictive models;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-4120-7

Type

conf

DOI

10.1109/ACSSC.1993.342340

Filename

342340