Analog implementation of SNR based gain adaptation for denoising

Author

Malladi, Krishna T. ; Anderson, David V.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India

fYear

2009

fDate

24-27 May 2009

Firstpage

269

Lastpage

272

Abstract

In the current work, a novel analog hardware to denoise speech signals has been proposed and simulated in 0.5 mum VLSI technology. The system is based on Automatic Gain Control which suppresses the noisy parts while boosting clean intervals of a signal. Further, the architecture is devised using Operational Transconductance Amplifiers (OTA) operating in sub-threshold region for attaining high programmability, low power and also to facilitate testing on an RASP 2.7 FPAA Prototype. A test noisy signal of 5 dB SNR when applied to the system resulted in a 13.5 dB improved output SNR consuming 0.53 mW power from a 1.6 V supply.

Keywords

VLSI; analogue integrated circuits; automatic gain control; field programmable analogue arrays; interference suppression; low-power electronics; operational amplifiers; signal denoising; speech processing; OTA; RASP 2.7 FPAA Prototype; SNR based gain adaptation; VLSI technology; analog hardware implementation; automatic gain control; noise suppression; operational transconductance amplifier; power 0.53 mW; size 0.5 mum; speech signal denoising; sub-threshold region; voltage 1.6 V; Boosting; Gain control; Hardware; High power amplifiers; Noise reduction; Operational amplifiers; Speech; Testing; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5117737

Filename

5117737