Title :
ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor
Author :
Renaudin, M. ; Vivet, P. ; Robin, F.
Author_Institution :
ENST de Bretagne, Brest, France
fDate :
30 Mar-2 Apr 1998
Abstract :
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving desynchronized units. The design flow and circuit style are an original application of A. Martin´s method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 μm technology
Keywords :
CMOS integrated circuits; microprocessor chips; real-time systems; reduced instruction set computing; 16 bit; ASPRO-216; CMOS integrated circuits; circuit style; design flow; desynchronized units; embedded applications; scalar processor; standard-cell QDI 16-bit RISC asynchronous microprocessor; Arithmetic; Asynchronous circuits; Design methodology; Energy consumption; Lapping; Microprocessors; Reduced instruction set computing; Registers; Telecommunications; Very large scale integration;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on
Conference_Location :
San Deigo, CA
Print_ISBN :
0-8186-8392-9
DOI :
10.1109/ASYNC.1998.666491
