A simplified approach of wordlength estimation and its application

With the computation power of the state-of-the-art processors and digital electronics, fast microprocessors and combination-logic devices, such as CPLD and FPGA, have become dominant in control engineering. Engineers usually expect that designed controllers can be realized accurately with fast processing speed. However, though the speed of digital electronics has been increased dramatically in the past decade, the resolution has not been improved significantly. As the demand of precision control increases with faster response, calculated outputs of the synthesized controller with fast sample rate but insufficient resolution will not only be distorted, but it can also lead to undesired results or become unstable. This paper provides a guideline to estimate the required wordlength for digital controllers in state-space realization.