Area-efficient drawings of rectangular duals for VLSI floor-plan

The authors consider the problem of finding the most area-efficient floorplan for macro cell (or general cell) layout, which satisfies all the constraints imposed not only on the area and the aspect ratio of each block but also on the length of the abutment between blocks. The floorplanning is implemented on the assumption that the relative position of each block has been specified in terms of a rectangular dual. The main task is composed of two algorithms; one is to find an area-efficient drawing of a rectangular dual D under these constraints, and the other is to estimate a lower bound to the area required to draw D. Using these algorithms together with the one to enumerate all rectangular duals, a floorplanning scheme is described.<>