Title :
A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS
Author :
Hiraku, Y. ; Hayashi, Isao ; Hayun Chung ; Kuroda, Tadahiro ; Ishikuro, Hiroki
Author_Institution :
R&D Dept., Semicond. Technol. Acad. Res. Center (STARC), Tokyo, Japan
Abstract :
This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μW at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/MHz. The core area is 0.037mm2.
Keywords :
CMOS digital integrated circuits; VHF circuits; digital phase locked loops; integrated circuit design; low-power electronics; radiofrequency integrated circuits; radiofrequency oscillators; time-digital conversion; 8-phase digitally controlled ring oscillator; CMOS technology; TDC; delay-line; frequency 10 MHz to 100 MHz; low- power all-digital PLL; power 45.5 muW; power consumption; power scalable AD-PLL; size 40 nm; time-to-digital converter; ultralow-voltage all-digital PLL; voltage 0.5 V;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522616
