Neural network implementation using distributed arithmetic

Deals with the direct hardware implementation of trained neural networks and suggests a matrix-vector multiplier synthesis method which makes possible very efficient hardware realization. The full parallel, bit-serial architecture can be efficiently used for FPGA and ASIC implementations. The new neural network realization approach can be integrated into automatic neural design environments. The algorithm is based on bit-level optimization and signal flow graph reduction/merging. The new synthesis approach results in significant hardware cost saving and increases the operating speed by decreasing the average fan-out which allows higher clock rate. This result is achieved without any precision loss during the computation