An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter

Most of the methods for analyzing and designing algorithm-based fault-tolerant (ABFT) systems assume that redundant computations and checking operations are computed by fault-free processors. However, the redundant computations and the checking operations are usually a part of the ABFT system in practical applications, and are needed to be performed on the system processors so that the system still maintains the desired fault tolerance. To achieve these objectives, we extend the MPDC graph model, which has been used for representing ABFT systems, to handle redundant computations, checking operations and their mapping to processors concurrently with nominal computations. A single-fault locatable FIR filter based on the extended MPDC graph model is synthesized on a systolic array as a practical implementation of the proposed method